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rev. prc information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. features 8 channel 24 - bit simultaneous sampling adcs sample rate converter (src) for coherent sampling adjustable phase synchronization pga per channel (gain 1 , 2, 4, 8 ) low i nput bias current: 6 na single ended o r true differential inputs 128 ksps output d ata rate/per channel internal 2.5 v reference optimize power dissipation & performance two power mode s: hi gh resolution mode low power mode low latency sinc 3 and sinc5 filter path s low resolution sar adc fo r system and chip diagnostics power supply bi polar ( 1.65 v supply) or unipolar ( 3.3 v supply) supply digital /io supply 1.8 v to 3.6 v performance t emperature range : C 40c to +1 0 5c functional temperature range: C 40c to +1 2 5c perfo rmance combined ac & dc performance 112db snr/ dynamic range at 8 ksps -1 08 db thd 15ppm inl, 25 0 uv offset error, 0.1 % gain e rror 5 ppm/c typ internal reference tempco applications power quality and measurement applications general purpose data acquisition applications industrial process control applications functional block diagram figure 1 a d7771 functional block diagram 8- ch, 24 - bit simultaneous sampling adc preliminary technical data AD7771 one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2015 analog devices, inc. all rights reserved.
AD7771* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? AD7771 evaluation board documentation application notes ? an-1388: coherent sampling for power quality measurements using the ad7779 24-bit simultaneous sampling sigma-delta adc ? an-1392: how to calculate offset errors and input impedance in adc converters with chopped amplifiers ? an-1393: translating system level protection and measurement requirements to adc specifications data sheet ? AD7771: 8-channel, 24-bit simultaneous sampling adcs preliminary data sheet software and systems requirements ? ad7770/AD7771/ad7779 - no-os driver tools and simulations ? ad7770/AD7771/ad7779 filter model ? AD7771 crc calculator ? ad7770/AD7771/ad7779 ibis model reference materials press ? analog devices improves monitoring and protection of smart grid transmission and distribution equipment design resources ? AD7771 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all AD7771 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
rev. prc | page 2 of 13 table of contents f eatures .............................................................................................. 1 power supply ..................................................................................... 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 3 specifications ..................................................................................... 4 absolute maximum ratings ........................................................9 thermal resistance .......................................................................9 esd caution ....................................................................................9 pin configuration and function descriptions ......................... 10 AD7771 preliminary technical dat a
rev. prc | page 3 of 13 general description the AD7771 is a n 8 - channel simultaneously sampled, analog - to - digital converter. there are 8 full sigma delta adcs on - chip. the AD7771 provides a high input impedance to allow for direct sensor connection. each input channel has a programmable gain stage catering for gains of 1,2,4,8 to map lower amplitude sensor outputs into the full scale adc input range to maximize the dynamic range of the signal chain. the analog inputs can accept unipolar 0 to 2.4 v or true bipolar 1.25v analog input signals with 3.3v or 1.65v anal og supply voltages respectively. the analog inputs can be configured to accept true differential or single - ended signals to match different sensor output configurations. each channel contains an adc modulator and sinc 3 /sinc 5 low latency digital filter s. a sampl e rate converter (src ) is provide d to allow fine resolution control over the AD7771 output data rate (odr). this can be used in power quality applications where the odr resolution is required to maintain coherency with 0.01hz changes in the line fr equency. the s rc can be programmed through the spi interface. the AD7771 implements two different interfaces, data output interface and a spi control interface. the adc data output interface is dedicated to transmitting the adc conversion results from the AD7771 to the processor , acting as a master . the spi interface is used to write to and read from the AD7771 configuration registers and for the control and reading of data from the sar adc. the spi interface can also be configure to output the sigma delt a conversion data . the AD7771 includes a 1 2- bit sar adc. this adc can be used for AD7771 diagnostics without having to decommission one of the sigma delta adc channels dedicated to system measurement functions. with the use of an external multiplexer and s ignal conditioning, the sar adc can be used to validate the sigma delta adc measurements in applications where functional safety is required. in addition, the AD7771 offers three gpios that can be used to control an external multiplexer. the AD7771 contai ns a 2.5v reference and reference buffer. the reference has a temperature co - efficient of 20 ppm/c max. the AD7771 offer s two modes of operation: high resolution m ode and low power mode. the high resolution mode provides h igher d ynamic r ange while co nsuming 13 mw/ch and the low power mode consumes just 5 mw/ch at a reduced dynamic r ange specification. the specified operating temperature range is - 40c to +105c while the part is operational up to +125 c . in put referred noise for sinc 3 and sinc5 f ilters, sinc5 odr bw g ain1(uvrms/uvpp) gain2(uvrms/uvpp) gain4(uvrms/uvpp) gain8(uvrms/uvpp) 128k 26098 30.20 22.80 19.20 17.20 64k 14122 13.70 10.10 8.28 7.46 32k 7215 7.40 4.79 3.63 3.14 16k 3627.5 4.65 2.74 1.87 1.54 8k 1816.2 3.17 1.79 1.17 0 .93 4k 908.5 2.23 1.25 0.79 0.63 sinc3 odr bw g ain1(uvrms/uvpp) gain2(uvrms/uvpp) gain4(uvrms/uvpp) gain8(uvrms/uvpp) 32k 10045 11.91 7.00 4.79 3.84 16k 5076.2 5.60 3.35 2.37 1.99 8k 2545 3.64 2.10 1.42 1.15 4k 1273.5 2.51 1.42 0.93 0.74 2k 636 .75 1.77 0.99 0.64 0.51 1k 318.5 1.25 0.71 0.45 0.36 preliminary technical data AD7771
rev. prc | page 4 of 13 specifications avdd1x/avssx = 1.65v, 3.3v/agnd, avdd2 - avs sx = 2.2 v to 3.6v; iovdd = 2.3v to 3.6v; dgnd = 0v, ref = 2.5 v internal/external, mclk = 8192 khz for high resolution mode and 4 096 khz for low power mode, odr = 128 khz high resolution (hr) mode, odr = 32 khz low power (lp) mode; all specifications t min to t max , unless otherwise noted. table 1. specification table parameter test conditions comment min typ max unit analog inputs differential input voltage range vref = (ref+ ? ref?) v ref/pga gain v single - ended input voltage range 0 0to vref/ pga gain v common - mode input range av ss + 0.10 (avdd1? avss)/2 avdd 1 C 0.10 v absolute ain voltage limits avss + 0.10 avdd 1 C 0.10 dc input current hr, mclk=8192 kh z 6 na l p, mclk=4096 kh z 2.5 na differential bias current hr 3 na lp 1 na input current drift tbd a/ c input capacitance 8 pf pf pga gain settings 1,2, 4,8 gain dr ift 3 ppm/c bandwidth small signal 32 khz la rge signal hr mode 10 khz la rge signal lp mode 3 khz reference internal output voltage ref_out ? 0. 2% 2.5 +0.2% v initial accuracy t a = 25 c ?5 mv ref_out +5 mv v temperature coefficient - 40c < t a < + 105 c 5 ppm/c reference load current i l ? 10 + 10 ma dc power supply rejection (line regulation) 95 db load regulation ?v out /?i l 100 v/ ma voltage noise e n p-p , 0.1 hz to 10 hz 6.8 v rms voltage noise density e n 1khz, 2.5 v reference 273.5 nv /hz turn - on settling time 10 0n f 1.5 m s long - term stability 1000 hours tbd ppm external input voltage ref_in = (ref+) C (ref?) 1 2.5v avdd1x v buffer headroom av ss + 0 .1 av dd1x ? 0.1 ref? input voltage avss avdd1x C refx+ v average ref current current per channel ref buf disabled, hr mode 18 a/ v ref buf pre - q, h r mode 200 n a/v ref buf disabled, lp mode 4.5 a/ v ref buf pre - q, lp mode 100 na/ v ref buf enabled 120 na/ v temperature range specified performance t min to t max ? 40 +105 c AD7771 preliminary technical dat a
rev. prc | page 5 of 13 parameter test conditions comment min typ max unit functional t min to t max ? 40 +12 5 c tempertaure sensor accuracy 2 c digital filter response sinc 3 group delay see sc r details settling time see cr c details pass - band - 0.1 db see cr c details -3 db see cr c details decimation rate 16 4095.99 sinc 5 group delay see cr c details settling time see cr c details p ass - band - 0.1 db see cr c details -3 db see cr c details decimation rate 16 2048 clock source frequency high resolution mode tbd 8.192 mhz low power mode tbd 4.096 input low voltage, v il xtal 1 0.4 v x tal 2 input high volt age, v ih xtal1 tbd v x tal 2 duty cycle 45:55 50:50 55: 45 % input current ? 10 +10 a ? adc speed & performance resolution 24 bits output data rate (odr) high resolution mode 128 ksps low p ower mode 32 ksps no missin g code odr < 25 ksps 24 noise shorted input sinc 5 hig h resolution mode 70 nv/ hz low p ower mode 160 nv/ hz sinc 3 hig h resolution mode 85 nv/ hz low p ower mode 190 nv/ hz ac accuracy dynamic range shorted input s db sinc5 128 ksps , hr mode 96 32 k sps, hr mo de , 103 32 k sps , lp mode 96 8 k sps, lp mo de 104 sinc 3 16 ksps , hr mode 103 4 k sps, hr mo de 115 preliminary technical data AD7771
rev. prc | page 6 of 13 parameter test conditions comment min typ max unit 8 ksps, lp mode 110 2 ksps , lp mode , 118 thd hr -109 db lp -106 sinad 106 sfdr 107 db imd f a = 50 hz, f b = 5 1 hz , hr 125 db f a = 50 hz, f b = 5 1 hz , lp 105 dc power supply rejection avdd1x = 3.3v -90 db dc common mode rejection ratio 80 db crosstalk up to 2 khz input. reference buf fer full mode -11 0 db dc accuracy integral nonlinearity end point method 7 15 ppm/ f sr offset error 40 250 v offset error drift 0.5 v/c versus time tbd nv/ 1000 hrs offset matching 30 v gain error pga gain = 1 0.1% f s gain drift vs. temperature 150 ppm/ c gain matching 0.1 % sar adc speed & performance resolution 12 bits analog input range avs s4+0.1 avdd4 - 0.1 v analog input common mode range avs s4+0.1 (avdd4 -avss4)/2 avdd4 - 0.1 v analog input leakage current 10 na throughput 256 ksps tue dc accuracy differential mode inl lsb dnl no missing codes (12 bit) 1.5 lsb offset 1 lsb gain 0.6 lsb tue tbd lsb ac performance snr 1 khz 66 db thd 1 khz -83 db vcm pin output (av dd1? avss)/2 v load current i l 1 m a load regulation ?v out /?i l 12 v/ma short circuit current 5 ma logic inputs input high voltage, v inh 1.65v io vdd 1.95 v 0.65 iovdd v AD7771 preliminary technical dat a
rev. prc | page 7 of 13 parameter test conditions comment min typ max unit 2.3v io vdd 3.6 v 0.7 iovdd v input low voltage, v inl 1.65v io vdd 1.95 v 0.35 iovdd v 2.3v io vdd 3.6 v 0.4 v hysteresis 2 0.2 % io vdd <2.7v 0.1 % input currents -10 +10 a logic output (dout/ rdy , dclk, sdout , gpio ) output high voltage, v oh iovdd 3v, i source = 1ma 0.8 iovdd v 2.3 iov dd < 3v, i source 500 a 0.8 iovdd v iovdd < 2.3v, i source = 200 a 0.8 iovdd v output low voltage, v ol iovdd 3v, i sink 2 ma 0.4 v 2.3 io vdd <3v, i sink 1 ma 0.4 v iovdd < 2.3v, i sink 100 a 0.4 v leakage cu rrent floating state -10 + 10 a output capacitance floating state 10 pf ? data output coding 2 s com p sar data output coding binar y power supplies all ? channels enabled cmos clock, avdd 1 x/avdd 2 x/avdd 4 = 3.3 v, iovdd = 1.8 v a vdd1 x ? avss 3.0 3.6 v i_avdd1x 1 2 reference buffer pre -q , vcm enable, internal reference enable hr 17 lp 4.5 ma refer ence buffer enable , vcm enabled, i nternal reference enabled ma hr 19 lp 5 ma refer ence buffer disable , v cm disable d, internal reference d isable d ma hr 13 lp 3.5 ma avdd2 C avss 2.2 3.6 v i_avdd2x hr 9 ma lp 3.5 ma avdd4 C avss4 avdd 1 x 3.6 iavdd 4 sar enable, 256 ksps 1.6 ma sar disable 0.05 ua avss - dgnd - 1.8 0 v preliminary technical data AD7771
rev. prc | page 8 of 13 parameter test conditions comment min typ max unit iovdd ? dgn d 2 3.6 v i _ iovdd cmos clock, hr 7.5 ma cmos clock, lp 2.5 power dissipation reference buffers preq, vcm enabled, internal reference disabled, osc enabled, sar disabled hr 99 mw lp 31.5 mw refer ence buffers off, vcm disabled, inte rnal reference disabled, osc disabled, sar disabled hr 85.5 mw lp 27.5 mw power down all adcs disable tbd w 1 avddx = 3.3v, avssx = gnd, iovdd = 1.8v, cmos clock 2 disabling either vcm or internal reference would lead to a 40ua current consumption reduction AD7771 preliminary technical dat a
rev. prc | page 9 of 13 absolute maximum rat ings table 2. absolute maximum ratings parameter rating avddx to avss x ? 0.3 v to + 3.96v avss x to d gnd ? 1.98 v to +0.3 v aregxcap to avssx ? 0.3 v to + 1.98 v dregcap to dgnd ? 0.3 v to + 1.98 v iovdd to dgnd ? 0.3 v to + 3.96v iovdd to avssx ? 0.3 v to +5.94 v avss4 to avssx avdd1x ? 0.3 v to + 3.96v analog input voltage avssx ? 0.3 v to a vdd1x +0.3 v or +3.96v (whichever is less) refx input voltage avssx ? 0.3 v to avdd 1x +0.3 v or +3.96v (whichever is less) auxin+/auxin - avssx ? 0.3 v to avdd 4 +0.3 v or +3.96v (whichever is less) digital input voltage to dgnd dgnd ? 0.3 v to iovdd + 0.3 v or +3.96v (whichever is less) digital output voltage to dgnd dgnd ? 0.3 v to iovdd + 0.3 v or +3.96v (whichever is less) xtal1 to dgnd dgnd ? 0.3 v to dregcap + 0. 3v or +1.98v (whichever is less) ain/digital input current tbd ma operating temperatur e range ? 40c to +1 2 5c junction temperature, (t j maximum) +15 0 c storage temperature range ? 65 c to +1 50c reflow soldering 260c esd 2kv ficdm corner pins ( 1 , 16, 17, 32, 33, 48 , 49, 64 ) +750v others +500v stresses above those listed under ab solute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposu re to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance thermal performance is directly linked to pcb design and operating environment. close attention to pcb thermal design is required. table 3 . thermal resistance package type ja jb jt jb units 64-cp -15 1 30.43 0.13 6.59 c /w 64-cp -15 2 22.62 3.17 0.09 3.19 c/w 1- thermal impedance simulated values are based on jedec 2s2p thermal test board with no thermal vias. see jedec jesd51. 2- thermal impedance simulated values are based on jede c 2s2p thermal test board with 49 thermal vias. see jedec jesd51. esd caution preliminary technical data AD7771
rev. prc | page 10 of 13 pin configuration and function descriptions figure 2 . pin description AD7771 preliminary technical dat a
rev. prc | page 11 of 13 table 4 . pin description pin no. mnemonic type direction description 1 ain0 - a nalog input input analog input channel 0 2 ain 0+ a nalog input input analog input channel 0 3 ain1 ? a nalog input input analog input channel 1 4 ain1+ a nalog input input analog input channel 1 5 avss 1a supply supply negative front end analog supply for channels 0 to 3, typical ? 1.65v(dual supply), and agnd (single supply). connect all avssx pins to the same potential 6 avdd 1a supply supply positive front end analog supply for channels 0 to 3, typical avssx + 3.3v. this pin should be connected together with avdd1b. 7 ref 1 ? reference input negative reference input for channels 0 to 3 , typical avssx. connect all refx ? pins to the same potential 8 ref1+ reference input positive reference input 1 for channels 0 to 3, typical ref1 ? + 2.5v 9 ain 2 ? a nalog input input analog input channel 2 10 ain2+ a nalog input input analog input channel 2 11 ain3 ? an alog input input analog input channel 3 12 ain3+ a nalog input input analog input channel 3 13 mode0 / gpio 0 digital i/o io pin control mode: mode0 input pin, s pi control mode: configurable gpio0 . if this pin is not used, connect to dgnd or iovdd . 14 mode1 / gpio 1 digital i/o io pin control mode: mode1 input pin spi control mode: configurable gpio1 . if this pin is not used, connect to dgnd or iov dd . 15 mode2 / gpio 2 digital i/o io pin control mode: mode2 input pin, spi control mode: configurable gpio2 . if this pin is not used, connect to dgnd or iovdd . 16 mode3/alert digital i/o io pin contro l mode: mode3 input pin, spi control mode: alert output pin 17 convst_sar digital input input pin control mode output interface selection s pi control mode - sar convert start 18 alert/ cs digital input input pin control mode: alert output pin spi control mode: chip select 19 dclk2 / sclk digital input input pin control mode: dclk frequency selection, spi control mode: spi clock. 20 dclk1 / sdi digital input input pin control mode: d clk frequency selection spi control mode: spi data in . connect this pin to dgnd if the part is configured in pin contro mode with spi as data output interface 21 dclk 0 / sdo digital output output pin control mode: dclk frequency selection spi control mode: spi data out 22 dgnd supply supply digital ground 23 dr egcap supply output digital ldo output. decouple to dgnd with 1 uf cap 24 iovdd supply supply io digital levels and dldo supply , fro m 1.8v to 3.6v. iovdd should not be lower than dregcap. 25 dout 3 digital output io data output pin 3. if the part is configured in daisy - chain mode, this pin acts as an input pin . preliminary technical data AD7771
rev. prc | page 12 of 13 p i n no. mnemonic type direction description 26 dout 2 digital output io data output pin 2. if the part is configured in daisy - chain mode, this pin acts as an input pin . 27 dout 1 digital output output data output pin 1 28 dout 0 digital output o utput data output pin 0 29 dclk digital output output data output clock 30 drdy digital output output data output ready 31 xtal 1 clock input xtal 1 input connection , if cmos is used as a clock source, connect tie this pin to dgnd. 32 xtal 2 /mclk clock input xtal2 input connection or cmos clock 33 start digital input input synchronization puls e. this pin is used to synchronize internally an external start asynchronous pulse with mclk. the synchronize signal is shift out by sync_out pin .tie to dgnd is not used. 34 sync_out digital output input s ynchronization signal . this pin generates a synchronous pulse 35 sync_in digital input input sync_in reset the internal sinc filters. 36 reset digital input input asynchronous reset pin. resets all registers to default value . i 37 ain 7 + a nalog input input analog input channel 7 38 ain 7 ? a nalog inpu t input analog input channel 7 39 ain 6 + a nalog input input analog input channel 6 40 ain 6 ? a nalog input input analog input channel 6 41 ref2+ reference input positive reference input 1 for channels 4 to 7, recommended value ref2 ? + 2.5v 42 ref2 ? ref erence input negative reference input for channels 4 to 7, typically avssx. connect all refx ? pins to the same potential 43 avdd1 b supply supply positive front end analog supply for channels 4 to 7. this pin should be connected together with avdd1a 44 av ss1b supply supply negative front end analog supply for channels 4 to 7 , typical - 1.65 v(dual supply) or agnd (single supply). connect all avssx pins together 45 ain 5 + a nalog input input analog input channel 5 46 ain 5 ? a nalog input input analog input channel 5 47 ain4+ a nalog input input analog input channel 4 48 a in4 ? a nalog input input analog input channel 4 49 ref_ out reference output 2.5v reference output 50 avss 2 b supply supply negative analog supply . connect all avssx pins together. 51 ar eg 2 cap supply output analog ldo output . decouple to avss 2 with 1 uf cap 52 avdd 2 b supply supply positive analog supply , this pin should be connected together with avdd2a 5 3 avss 3 supply supply negative analog ground . connect all avssx pins together 54 fo rmat 1 digital input input output data frame, 55 format 0 digital input input output data frame, 56 clk_sel digital input input select clock sou rce, 57 vcm analog output output common mode voltage output, (av dd1? avs s)/2 58 avdd 2a supply input analog supply , from 2.2v to 3.6v. avss2x should not be lower than aregxcap. avss2x should not be l ower than aregxcap.connected this pin should be connected together with avdd2b 59 areg 1 cap supply output analog ldo output . decouple to avss with 1uf cap . AD7771 preliminary technical dat a
rev. prc | page 13 of 13 p i n no. mnemonic type direction description 60 avss 2b supply input negative analog supply . connect all avssx together 61 avss 4 supply suppl y negative sar analog supply and reference. connect all avssx together 62 avdd 4 supply supply positive sar analog supply and reference source, supply range from avdd1x to 3.6v 63 auxain + a nalog input input sar analog input channel 64 auxain - a nalog inp ut input sar analog input channel preliminary technical data AD7771 ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr13802-0-10/15(prc)

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